Workers are aware of computer systems having a pair of processor units such as processors CPU-A, CPU-B in FIG. 1. Here, it will be understood, that each processor has equal ability to access all system resources and access is granted on an alternating basis by an arbiter unit ARB. When the system is reset, or power is applied, the processors begin a procedure known as Power-On Self-Test (POST), in which the system is tested and initialized, including memory and chipset registers.
Only one processor is allowed to execute POST, as the code is not reentrant, and having both processors modifying registers and memory independently would cause problems. In addition, if both processors are executing and accessing off-cpu resources, the system will run only half as fast as if one processor were halted.
Another problem involves assigning certain AT-compatible resources to the ("boot") processor which is executing POST. The A20-mask and the port92/keyboard controller reset function must be available to this (boot) processor, but should not be available to the other processor.
Such problems could be alleviated by always allowing the same processor to start POST (let one always be the "boot processor"), while holding the other in some reset or halted state, but this wouldn't afford any flexibility or resiliency; e.g., if the so-designated boot processor failed to start executing, for whatever reason. Thus, it is desirable to allow either processor to execute POST--and such is a salient object hereof.
We propose resolving such problems by using "semaphore" means, whereby each processor must check the semaphore to see if the other has already begun executing POST. The processor that first accesses (captures) the semaphore is allowed to continue, while the other must be prevented from executing POST.
A "memory-based semaphore" is not feasible since the memory has not been initialized. Only one processor should perform the initialization, since it involves writing to chipset configuration registers, so memory cannot be set up to allow the semaphore to reside there. A semaphore based on a standard I/O port will not work because there are no locked cycles to I/O ports: thus, if one processor sees the semaphore as "clear", then before it can "set" the semaphore the other processor might also see it as clear, leading to both processors executing. In addition, neither memory-based nor standard I/O port-based methods allow the assignment of A20-mask and reset to the boot processor.